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Features
* * * * *
Available in Gate Array or Embedded Array High-speed, 150 ps Gate Delay, 2-input NAND, FO = 2 (nominal) Up to 2.7 Million Used Gates and 976 Pins 0.35 Geometry in up to Four-level Metal System-level Integration Technology - Cores: ARM7TDMITM RISC Microprocessor; AVR(R) RISC Microcontroller; OakDSPCoreTM, TeakTM and PalmDSPCoreTM Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284, CAN Cores and Other Assorted Processor Peripherals - Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs, and PORs - Soft Macro Memory: Gate Array SRAM -- ROM -- DPSRAM -- FIFO - Hard Macro Memory: Embedded Array SRAM -- ROM -- DPSRAM -- FIFO -- E2 -- Flash - I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 20 mA @3.3V; 2.5V Native I/O, 3.3V Native I/O, 5.0V Tolerant/Compliant I/O
ASIC ATL35 Series
Description
The ATL35 Series ASIC family is fabricated on a 0.35 CMOS process with up to four levels of metal. This family features arrays with up to 2.7 million routable gates and 976 pins. The high density and high pin count capabilities of the ATL35 family, coupled with the ability to add embedded microprocessor cores, DSP engines and memory on the same silicon, make the ATL35 series of ASICs an ideal choice for system-level integration. Figure 1. ATL35 Gate Array ASIC
Figure 2. ATL35 Embedded Array ASIC
Standard Gate Array Architecture
Analog
Rev. 0802F-ASIC-05/02
1
Table 1. ATL35 Array Organization
Device Number ATL35/44 ATL35/68 ATL35/84 ATL35/100 ATL35/120 ATL35/132 ATL35/144 ATL35/160 ATL35/184 ATL35/208 ATL35/228 ATL35/256 ATL35/304 ATL35/352 ATL35/388 ATL35/432 ATL35/484 ATL35/540 ATL35/600 ATL35/700 ATL35/800 ATL35/900 ATL35/976 Notes: 4LM Routable Gates(1) 4,195 13,230 22,200 33,480 47,839 59,185 71,737 90,514 121,877 150,085 182,880 233,774 334,044 425,958 520,695 652,421 768,033 964,078 1,196,371 1,642,242 1,999,526 2,542,995 2,767,931 3LM Routable Gates(1) 3,729 11,760 19,734 29,760 42,211 52,222 63,298 79,866 107,538 131,324 160,020 204,552 292,288 369,164 451,269 565,431 658,314 826,353 1,025,460 1,407,636 1,691,906 2,151,765 2,306,609 Available Routing Sites(2) 6,216 19,600 32,890 49,600 75,042 92,840 112,530 141,984 191,180 250,142 304,800 389,624 556,740 757,260 925,680 1,159,860 1,462,920 1,836,340 2,278,802 3,128,080 4,101,592 5,216,400 6,150,958 Max Pad Count 44 68 84 100 120 132 144 160 184 208 228 256 304 352 388 432 484 540 600 700 800 900 976 Max I/O Count 36 60 76 92 112 124 136 152 176 200 220 240 288 336 372 416 468 516 576 676 776 876 952 Gate Speed(3) 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps 150 ps
1. One gate = NAND2 2. Routing site = 4 transistors 3. Nominal 2-input NAND gate FO = 2 at 3.3V
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Design
Atmel supports several major software systems for design with complete cell libraries, as well as utilities for netlist verification, test vector verification and accurate delay simulations. Table 2. Design Systems Supported
System Cadence Design Systems, Inc.
(R)
Tools Opus - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator BuildGatesTM - Synthesis (Ambit) ModelSim(R) - Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Generation PrimeTimeTM - Static Path VCSTM - Verilog Simulator Floorplan ManagerTM Debussy(R) First Encounter(R)
TM
Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 5.2 01.08-SP1 5.1 v2001.2.3
Mentor Graphics(R) SynopsysTM
Novas Software, Inc. Silicon PerspectiveTM
Design Flow and Tools
Atmel's ASIC design flow is structured to allow the designer to consolidate the greatest number of system components onto the same silicon chip, using widely available thirdparty design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage and process, and includes the effects of metal loading, interlevel capacitance, and edge rise and fall times. The design flow includes clock tree synthesis to customer-specified skew and latency goals. RC extraction is performed on the final design database and incorporated into the timing analysis. The ASIC Design Flow, shown on page 4, provides a pictorial description of the typical interaction between Atmel's design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning and scan insertion activities. Leading-edge tools from vendors such as Synopsys and Cadence are fully supported in our design flow. In the case of an embedded array design, Atmel will conduct a design review with the customer to define the partition of the embedded array ASIC and to define the location of the memory blocks and/or cores so an underlayer layout model can be created. Following database acceptance, automated test pattern generation (ATPG) is performed, if required, on scan paths using Synopsys tools; the design is routed; and postroute RC data is extracted. After post-route verification and a final design review, the design is taped out for fabrication.
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Table 3. Design Flow
Deliver Design Kit
Kickoff Meeting
If Embedded Array
Define Underlayer
Synthesis/ Design Entry
Scan/JTAG
Simulation/ Static Path
Floorplan
If Embedded Array (Preliminary Netlist)
Create Underlayer
Database Handoff
Tape Out Underlayer
Database Acceptance
Fabricate Underlayer
Place and Route/ Clock Tree
Verification/ Resimulation
Final Design Review If Standard Cell If Embedded/Gate Array
Tape Out Full Mask Set
Tape Out Metal Masks
Fabricate
Fabricate Personality
Customer Atmel Joint
Proto Assembly and Test Rev. 2.2-03/02
Proto Shipment
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Pin Definition Requirements
The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V compliant buffers, an appropriate number of pad sites must be reserved for the VDD5 pins, which are used to distribute 5V power to the compliant buffers.
Design Options
Logic Synthesis
Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synopsys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and VHDL, Atmel's preferred HDL format for ASIC design is Verilog.
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Macro Cores
AVR 8-bit RISC Microcontroller Core
The AVR RISC microcontroller is a true 8-bit RISC architecture, ideally suited for embedded control applications. The AVR is offered as a gate level, synthesizable macro core in the ATL35 family. The AVR supports a powerful set of 120 instructions. The AVR prefetches an instruction during a prior instruction execution, enabling the execution of one instruction per clock cycle. The Fast Access RISC register file consists of 32 general purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR can incorporate up to 64K x 16 program memory (ROM) and 64K x 8 data memory (SRAM). Among the peripheral options offered are: UART, 8-bit timer/counter, 16-bit timer/counter, programmable watchdog timer and SPI. Figure 3. AVR 8-bit RISC Microcontroller Core
N
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8-BIT DATA BUS
ARM7TDMI 32-bit RISC Microprocessor Core
The ARM7TDMI is a powerful 32-bit processor offered as a hard macro core in the ATL35 family. The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance with very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and an impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard lowpower logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard SRAMs. The ARM7TDMI core interfaces to several optional peripheral macros. Among the peripheral options offered are real-time clock, peripheral data controller, USART, external bus interface, interrupt controller, timer counter and watchdog timer. Figure 4. ARM7TDMI 32-bit RISC Microprocessor Core
Address Incrementor
,
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OakDSPCore(R) Digital Signal Processing Core
Atmel's hard macro OakDSPCore is a 16-bit, general purpose, low-power, low-voltage and high-speed Digital Signal Processor (DSP). Oak is designed for mid-to-high-end telecommunications and consumer electronics applications, where low-power and portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. Oak is available as a DSP core in Atmel's ASIC cell library, to be utilized as an engine for a DSP-based ASIC. It is specified with several levels of modularity in SRAM, ROM and I/O blocks, allowing efficient DSP-based ASIC development. Oak is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic and power management. The Oak core consists of three main execution units operating in parallel: the Computation/Bit-Manipulation Unit (CBU), the Data Addressing Arithmetic Unit (DAAU) and the Program Control Unit (PCU). The core also contains ROM and SRAM addressing units, and Program Control Logic (PCL). All other peripheral blocks that are application specific are defined as part of the user-specific logic and implemented around the DSP core on the same silicon die. Oak has an enhanced set of DSP and general microprocessor functions to meet most application requirements. The Oak programming model and instruction set are aimed at the straightforward generation of efficient and compact code.
Teak and PalmDSPCore(R) The Teak and Palm are synthesizable dual-MAC DSP cores from DSP Group, Inc. The Digital Signal Processing Teak is a fixed-point 16-bit DSP, whereas the Palm can be configured for 16-bit, 20-bit or 24-bit fixed-point math. Both cores are optimized for high MIPs per mW, with perforCores
mance targeted to handling filtering, voice compression/decompression and modem functions for portable and wireless applications such as 3G digital cellular. Hardware support is also provided for implementing Viterbi forward error correction. The Teak and Palm cores both have a comprehensive suite of development tools that are easy to learn and are intended to support rapid code development. A C compiler that supports in-line assembly language and provides language extensions to enhance C code optimization is provided. An assembler and linker are also provided. Both emulation (using test silicon) and source-level simulation of C and assembly language enhance software verification.
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ATL35 Series Cell Library
Atmel's ATL35 Series ASICs make use of an extensive library of cell structures, including logic cells, buffers and inverters, multiplexers, decoders and I/O options. Soft macros are also available. The ATL35 Series Phase Locked Loop (PLL) operates at frequencies of up to 400 MHz with minimal phase error and jitter, making it ideal for frequency synthesis of highspeed, on-chip clocks and chip-to-chip synchronization. Output buffers are programmable to meet the voltage and current requirements of PCI (20 mA) @3.3V. These cells are characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test silicon. Characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product.
Table 4. Cell Index
Cell Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI222 AOI2223 AOI2223H AOI222H AOI22H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T BUF8 BUF8T BUF12 Description 1-bit Full Adder with Buffered Outputs 2-input AND 2-input AND - High Drive 3-input AND 3-input AND - High Drive 4-input AND 4-input AND - High Drive 5-input AND 2-input AND into 2-input NOR Two 2-input ANDs into 2-input NOR Three 2-input ANDs into 3-input NOR Three 2-input ANDs into 3-input NOR - High Drive Two 2-input ANDs into 2-input NOR - High Drive 2-input AND into 2-input NOR - High Drive 2-input AND into 3-input NOR 1x Buffer 2x Buffer 2x Tristate Bus Driver with Active-high Enable 2x Tristate Bus Driver with Active-low Enable 3x Buffer 4x Buffer 4x Tristate Bus Driver with Active-high Enable 8x Buffer 8x Tristate Bus Driver with Active-high Enable 12x Buffer Gate Count 10 2 3 3 4 3 4 5 2 2 4 8 4 4 3 2 2 4 4 3 3 6 5 10 8
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Table 4. Cell Index (Continued)
Cell Name BUF16 CLA7X DEC4 DEC4N DEC8N DFF DFFH DFFBCPX DFFBSRX DFFC DFFCH DFFR DFFRQ DFFS DFFSR DLY1 DLY2 DLY3 DLY4 DSS DSSC DSSBCPY DSSBR DSSBS DSSCH DSSR DSSS DSSSR HLD1 INV1 INV1D INV1Q INV1TQ INV2 INV2T Description 16x Buffer 7-input Carry Lookahead 2:4 Decoder 2:4 Decoder with Active-low Enable 3:8 Decoder with Active-low Enable D Flip-flop D Flip-flop High Drive D Flip-flop with Asynchronous Clear and Preset with Complementary Outputs D Flip-flop with Asynchronous Set and Reset with Complementary Outputs D Flip-flop with Asynchronous Clear D Flip-flop with Asynchronous Clear - High Drive D Flip-flop with Asynchronous Reset Quad D Flip-flop with Asynchronous Reset D Flip-flop with Asynchronous Set D Flip-flop with Asynchronous Set and Reset Delay Buffer 1.0 ns Delay Buffer 1.5 ns Delay Buffer 2.0 ns Delay Buffer 4.5 ns Set Scan Flip-flop Set Scan Flip-flop with Asynchronous Clear - High Drive Set Scan Flip-flop with Clear and Preset Set Scan Flip-flop with Reset Set Scan Flip-flop with Set Set Scan Flip-flop with Asynchronous Clear - High Drive Set Scan D Flip-flop with Reset Set Scan D Flip-flop with Set Set Scan D Flip-flop with Set and Reset Bus Hold Cell 1x Inverter Dual 1x Inverter Quad 1x Inverter Quad 1x Tristate Inverter with Active-high Enable 2x Inverter 2x Tristate Inverter with Active-high Enable Gate Count 10 5 8 10 22 8 12 16 16 9 14 10 40 9 11 7 9 11 20 12 12 16 14 14 12 12 14 16 4 1 2 4 8 1 3
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Table 4. Cell Index (Continued)
Cell Name INV3 INV4 INV8 JKF JKFBCPX JKFC LAT LATB LATBG LATBH LATIQ LATR LATS LATSR MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H Description 3x Inverter 4x Inverter 8x Inverter JK Flip-flop Clear Preset JK Flip-flop with Asynchronous Clear and Preset and Complementary Outputs JK Flip-flop with Asynchronous Clear LATCH LATCH with Complementary Outputs LATCH with Complementary Outputs and Inverted Gate Signal LATCH with High-drive Complementary Outputs Quad LATCH with Inverted Output LATCH with Reset LATCH with Set LATCH with Set and Reset 2:1 MUX 2:1 MUX - High Drive 2:1 MUX with Inverted Output 2:1 MUX with Inverted Output - High Drive 2:1 MUX with Active-low Enable Quad 2:1 MUX with Active-low Enable Quad 2:1 MUX 3:1 MUX with Inverted Output 3:1 MUX with Inverted Output - High Drive 4:1 MUX 4:1 MUX with Transmission Gate Data Inputs 4:1 MUX with Transmission Gate Data Inputs - High Drive 5:1 MUX - High Drive 8:1 MUX 8:1 MUX with Active-low Enable 8:1 MUX with Transmission Gate Data Inputs - High Drive 2-input NAND Dual 2-input NAND 2-input NAND - High Drive 3-input NAND 3-input NAND - High Drive Gate Count 2 2 4 10 16 12 6 6 6 7 20 5 6 8 4 5 3 4 5 18 16 6 8 10 9 10 14 20 20 16 2 3 2 2 3
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Table 4. Cell Index (Continued)
Cell Name NAN4 NAN4H NAN5 NAN5H NAN5S NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR5S NOR8 OAI22 OAI222 OAI22224 OAI222H OAI22H OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Description 4-input NAND 4-input NAND - High Drive 5-input NAND 5-input NAND - High Drive 5-input NAND with Set 6-input NAND 6-input NAND - High Drive 8-input NAND 8-input NAND - High Drive 2-input NOR Dual 2-input NOR 2-input NOR - High Drive 3-input NOR 3-input NOR - High Drive 4-input NOR 4-input NOR - High Drive 5-input NOR 5-input NOR with Set 8-input NOR 2-input OR into 2-input NAND Two 2-input ORs into 2-input NAND Four 2-input ORs into 4-input NAND Two 2-input ORs into 2-input NAND - High Drive 2-input OR into 2-input NAND - High Drive 2-input OR into 3-input NAND 2-input OR 2-input OR - High Drive 3-input OR 3-input OR - High Drive 4-input OR 4-input OR - High Drive 5-input OR 2-input Exclusive NOR 2-input Exclusive NOR - High Drive 2-input Exclusive OR 2-input Exclusive OR - High Drive Gate Count 3 4 5 6 3 6 7 7 8 2 3 2 2 3 3 5 5 3 7 2 3 8 6 4 3 2 3 3 4 3 4 5 4 4 4 4
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Table 5. 3.3V I/O Buffer Cell Index
Cell Name PBATA100 PFDNOL PFDNOZ##L PFIPCI PFGTL PFGTLA PFICLK PFILVDSL PFILVDSLXR PFIVCOMPA PFIVREF PFOLVDS PFOLVDSH PFOZ## PFPECLL PFVSSCLEARA PFVSSCLEARC PFVSSCLEARD PIC PICH PICI PICS PICSI PICK PID PLL5_100 PLL5_400 PLL4_80N PO## PO##F PO##S PUSB PVDDREG PX1L Description Bidirectional ATA 100 Buffer High-speed, Low-voltage Differential Output Pair Impedance Controlled, High-speed, Low-voltage Differential Output Pair PCI Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer Clock Amplifier Input Buffer Low-voltage, Differential Input Pair Low-voltage, Differential Input Pair, External Resistor Low-speed, Low-power Comparator Voltage Reference Low-voltage, Differential Output Pair Low-voltage, Differential Output Pair, High Drive Impedance Controlled Output, ## = 25, 37, 50, 75 ohms Positive ECL Output Pair Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point CMOS Input CMOS Input, High Drive Inverting CMOS Input CMOS Input with Schmitt Trigger Inverting CMOS Input with Schmitt Trigger CMOS Input Buffer with Selectable Bus Hold Differential Input PLL Optimized for 20-100 MHz Output, External Bias PLL Optimized for 100-400 MHz Output, External Bias PLL Optimized for 80 MHz Output, Internal Bias Tristate Output Buffer; ## = 2, 4, ..., 24 mA Fast Tristate Output Buffer, ## = 2, 4, ..., 24 mA Slow Tristate Output Buffer, ## = 2, 4, ..., 24 mA Universal Serial Bus Interface Buffer Voltage Regulator Oscillator -- Max Frequency 2 MHz
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Table 5. 3.3V I/O Buffer Cell Index (Continued)
Cell Name PX2L PX3L PX4L Description Oscillator - Max Frequency 5 MHz Oscillator - Max Frequency 20 MHz Oscillator - Max Frequency 37 MHz
Table 6. 5.0V Tolerant I/O Buffer Cell Index
Cell Name PBATA100 PFIPCIV PFGTL PFGTLA PFIVREF PFVSSCLEARB PFVSSCLEARC PFVSSCLEARD PICV PICSV PLL5_100 PLL5_400 PLL4_80N PO##V PO##FV PO##SV PX1L PX2L PX3L PX4L Description 5V Tolerant Bidirectional ATA 100 Buffer 5V Tolerant PCI Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer Voltage Reference Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point 5V Tolerant CMOS Input Buffer 5V Tolerant CMOS Input with Schmitt Trigger PLL Optimized for 20-100 MHz Output; External Bias PLL Optimized for 100-400 MHz Output; External Bias PLL Optimized for 80 MHz Output; Internal Bias 5V Tolerant Tristate Output Buffer; ## = 2, 4, ..., 24 mA 5V Tolerant Fast Tristate Output Buffer; ## = 2, 4, ..., 24 mA 5V Tolerant Slow Tristate Output Buffer; ## = 2, 4, ..., 24 mA Oscillator - Max Frequency 2 MHz Oscillator - Max Frequency 5 MHz Oscillator - Max Frequency 20 MHz Oscillator - Max Frequency 37 MHz
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Table 7. 5.0V Compliant I/O Buffer Cell Index
Cell Name PFIPCIV5 PFGTL PFGTLA PFIVCOMPLS PFIVREF PFVSSCLEARB PFVSSCLEARC PFVSSCLEARD PICV5 PICSV5 PICKV5 PICSKV5 PLL5_100 PLL5_400 PLL4_80N PO##V5 PVDDREG PX1L PX2L PX3L PX4L Description 5V Compliant PCI Input Gunning Transceiver Logic Buffer Fast Output, Gunning Transceiver Logic Buffer 5V Compliant Low-speed, Low-power Comparator Voltage Reference Power-on Reset Power-on Reset, Higher Trip Point Power-on Reset, Lower Trip Point 5V Compliant CMOS Input Buffer 5V Compliant CMOS Input with Schmitt Trigger 5V Compliant CMOS Input Buffer with Selectable Bus Hold 5V Compliant CMOS Input Buffer with Schmitt Trigger and Selectable Bus Hold PLL Optimized for 20-100 MHz Output; External Bias PLL Optimized for 100-400 MHz Output; External Bias PLL Optimized for 80 MHz Output; Internal Bias 5V Tolerant Tristate Output Buffer; ## = 2, 4, ..., 24 mA Voltage Regulator Oscillator - Max Frequency 2 MHz Oscillator - Max Frequency 5 MHz Oscillator - Max Frequency 20 MHz Oscillator - Max Frequency 37 MHz
Absolute Maximum Ratings1
Parameter Operating Ambient Temperature Storage Temperature Maximum Input Voltage: Inputs 5V Tolerant/Compliant Maximum Operating Voltage (VDD) Maximum Operating Voltage (VDD5) Note: Rating -55C to +125C -65C to +150C VDD + 0.5V VDD5 + 0.5V 3.6V 5.5V
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Table 8. 2.5V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current High-level Input Voltage Buffer All All CMOS PCI CMOS PCI All PO11 PO11 CMOS VIH PCI CMOS Schmitt CMOS VIL VHYS VOH VOL Low-level Input Voltage Hysteresis High-level Output Voltage Low-level Output Voltage PCI CMOS Schmitt CMOS Schmitt PO11 PCI PO11 PCI IOH = 1.4 mA, VDD = VDD (min) IOH = -500 A IOL = 1.4 mA, VDD = VDD (min) IOL = 1.5 mA 0.7VDD 0.9VDD 0.4 0.1VDD 1.0 0.5 VIN = VDD or VSS, VDD = VDD (max), No pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 0.7VDD 0.475VDD 0.7VDD 1.5 0.3VDD 0.325VDD 0.3VDD V V V V V VIN = VSS, VDD = VDD (max) -10 -10 -10 9 6 10 VIN = VDD, VDD = VDD (max) Test Condition Min -55 2.3 2.5 Typ Max 125 2.7 10 10 Units C V A A A mA
Table 9. 3.3V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer All All CMOS PCI CMOS PCI All PO11 PO11 CMOS, LVTTL VIH High-level Input Voltage PCI CMOS/TTL-level Schmitt CMOS VIL Low-level Input Voltage PCI CMOS/TTL-level Schmitt Hysteresis TTL-level Schmitt 1.1 0.6 VIN = VDD or VSS, VDD = VDD (max), No pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 2.0 0.475VDD 2.0 1.7 0.8 0.325VDD 0.8 V V V VIN = VSS, VDD = VDD (max) -10 -10 -10 14 -9 10 VIN = VDD, VDD = VDD (max) Test Condition Min -55 3.0 3.3 Typ Max 125 3.6 10 10 Units C V A A A mA
VHYS
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Table 9. 3.3V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
VOH VOL High-level Output Voltage Low-level Output Voltage PO11 PCI PO11 PCI IOH = 2 mA, VDD = VDD (min) IOH = -500 A IOL = 2 mA, VDD = V DD (min) IOL = 1.5 mA 0.7VDD 0.9VDD 0.4 0.1VDD V V
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Table 10. 5.0V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD VDD5 IIH IIL IOZ IOS Parameter Operating Temperature Supply Voltage Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current Buffer All 5V Tolerant 5V Compliant CMOS CMOS All PO11V PO11V PICV, PICV5 VIH High-level Input Voltage PCI CMOS/TTL-level Schmitt PICV, PICV5 VIL Low-level Input Voltage PCI CMOS/TTL-level Schmitt Hysteresis High-level Output Voltage Low-level Output Voltage CMOS/TTL-level Schmitt PO11V PO11V5 PO11V, PO11V5 IOH = -1.7 mA IOH = -1.7 mA IOL = 1.7 mA 0.7VDD 0.7VDD5 0.5 1.1 0.6 VIN = VDD, VDD = VDD (max) VIN = VSS, VDD = VDD (max) VIN = VDD or VSS, VDD = V DD (max), No pull up VOUT = VDD, VDD = VDD (max) VOUT = V SS, VDD = VDD (max) 2.0 0.475VDD 2.0 -10 -10 8 -7 5.0 5.0 1.7 0.5VDD 0.8 0.325VDD 0.8 V V V V 5.5 5.5 V 10 Test Condition Min -55 3.0 4.5 3.3 5.0 Typ Max 125 3.6 5.5 10 Units C V V A A A
mA
VHYS VOH VOL
I/O Buffer DC Characteristics
Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 3.3V 3.3V 3.3V Typical 2.4 5.6 6.6 Units pF pF pF
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Testability Techniques
For complex designs involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs requires the use of more efficient testability techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-in self-test logic (in addition to functional test patterns) must be employed to provide both the user and Atmel with the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, a microprocessor or DSP engine or both, SRAM to support the microprocessor or DSP engine, and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high-performance digital tester. Combinations of parametric, functional and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and/or parametric testing can be performed. Since a digital tester must control all the clocks during the testing of an ASIC, provisions must be made for the VCO to be bypassed. Atmel's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test without impinging upon the normal functionality. In a similar vein, access to microprocessor, DSP and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. The ARM microprocessor, AVR microcontroller and OakDSPCore/TeakDSPCore/PalmDSPCore digital signal processors all support SCAN testing. SRAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins is a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that in almost all of these cases, the purpose of the testability technique is to give Atmel a means to assess the structural integrity of an ASIC, i.e., sort devices with manufacturing-induced defects. All of the techniques described above should be considered supplemental to a set of patterns that exercise the functionality of the design in its anticipated operating modes.
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0802F-ASIC-05/02
Advanced Packaging
The ATL35 Series ASICs are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays and ball grid arrays. High-volume onshore and offshore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. If a standard package cannot meet a customer's needs, a package can be designed to precisely fit the customer-specific application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations. Table 11. Packaging Options
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super BGA Low-profile BGA Chip-scale BGA Note:
(1)
Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 168, 204, 240, 256, 304, 352, 432, 560, 600 132, 144, 160, 180, 208 40, 49, 56, 64, 81, 84, 96, 100, 128
1. Partial List
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0802F-ASIC-05/02
Atmel Headquarters
Corporate Headquarters
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and AVR (R) are registered trademarks of Atmel. ARM7TDMI TM is a trademark of ARM Limited; OakDSPCoreTM , Teak TM and PalmDSPCore TM are trademarks of DSP Group; Cadence (R) is a registered trademark and OpusTM , NC Verilog TM, Pearl TM, Verilog-XL TM and BuildGates TM are trademarks of Cadence Design Systems, Inc.; MentorGraphics (R) and ModelSim (R) are registered trademarks and Leonardo Spectrum TM is a trademark of Mentor Graphics; Design CompilerTM , PrimeTime VCS TM Printed on recycled paper. and Floorplan Manager TM are trademarks and Synposys(R) and TetraMax(R) are registered trademarks of Synop(R) (R) (R) sys; Novas Software and Debussy are registered trademarks of Novas Software, Inc.; Silicon Perspective 0802F-ASIC-05/02 and First Encounter (R) are registered trademarks of Silicon Perspective. Other terms and product names may be the trademarks of others.

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